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Computer Science Colloquia

Monday, May 9, 2011
Ph.D. Qualifying Exam by Mario Marino
Advisor: Kevin Skadron
Attending Faculty: Kim Hazelwood; Sudhanva Gurumurthi; Westley Weimer

Olsson 236D, 23:00:00

RFDRAM:Addressing DRAM I/O pad scalability using RF Coplanar Waveguides on the Same Package

Offchip memory parallelism can be improved by having multiple memory controllers (MCs). However, the scalability of multiple MCs is limited by the number and area of I/O pads/pins allocated to them. Wire-based-radio-frequency (RF) is a technology that can benefit from the use of appropriate schemes of communication combined with a low latency media to address the scalability of MCs under I/O pads/pins constraints. In addition, it is a natural extension of CMOS and at this point it has lower costs and presents lower power than optics for distances up to 30cm. In this paper we propose a novel scalable RF-wire-based processor-to-memory organization in order to address the scalability of MCs and I/O pads by connecting the MCs to off-die DRAM ranks, all of them on the same package. The proposed organization is composed by RF transmitters, receivers, and RF quilt-packaging inter-die interconnection; we define RFMC as each MC that is connected to RF transmitters and receivers. In the proposed organization the MCs and DRAM ranks are directly connected to RFtransmitters and receivers, respectively on the processor and on the ranks' side. RF transmitters and receivers are responsible for modulating/demodulating data/address through quilt-packaging interconnection. Furthermore, we define RFpads as the number of quilt-packaging lines. We then show that using standard off-die on-package lower rate DDR2 memory ranks the proposed interface is able to scale bandwidth for up 16 outoforder(OOO) cores and 16 MCs using from 4 to 8 RFpads/MC. Assuming an electrical-based solution scaled under ITRS I/O pad count budget constraints as baseline, the use of RF can reduce memory latencies up 10%, increasing bandwidth up to 2x, while simultaneously reducing I/O pads area of up to 24.6%.