[an error occurred while processing this directive]

Skip to Content

Computer Science Colloquia

August 26, 2011
Wei Wang
Advisor: Jack Davidson
Attending Faculty: Mary Lou Soffa, Kevin Skadron, Sang Son

Olsson Hall, Room 236D, 2:00 PM

Ph.D. Qualifying Exam Presentation
Performance Analysis of Thread Mappings with a Holistic View of the Hardware Resources

ABSTRACT
With the shift to chip multiprocessors, managing shared resources has become a critical issue in realizing their full potential. Previous research has shown that thread mapping is a powerful tool for resource management. However, the difficulties of simultaneously managing multiple hardware resources and the varying nature of the workloads have impeded the efficiency of thread mapping algorithms. To overcome the difficulties of simultaneously managing multiple resources with thread mapping, this paper presents an in-depth analysis of the impact of different thread mappings on the application's performance and the resource's utilization. The analysis compares the importance of hardware resources in terms of thread mappings, which include L1 I/D-caches, I/D TLBs, L2 caches, hardware prefetchers, off-chip memory interconnects, branch predictors, memory disambiguation units and processor utilization. Additionally, the analysis provides guidelines for mapping threads to improve the utilization of individual resources when managing threads with different run-time characteristics. We also analyze how the relative importance of the resources varies depending on the workload characteristics. We show that by managing multiple resources based on priority and workload characteristics, thread mapping can improve an application's performance by up to 28% over contemporary Linux scheduler for the PARSEC benchmarks we examined, while the memory resources only provides performance improvement by up to 14%.